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| EL2021C EL2021C Monolithic Pin Driver Features Wide range of programmable analog output levels 0 5 Ampere output drive with external transistors Programmable Slew Rate Low overshoot with large capacitive loads-stable with 500 pF 3-state output Power-down capability Wide supply range Overcurrent sense General Description The EL2021 is designed to drive programmed voltages into difficult loads It has the required circuitry to be used as the pin driver electronics in board test systems Capable of overpowering logic outputs the part can accurately drive independently set high and low levels with programmed Slew Rates into reactive loads It can also be placed into high impedance to monitor the load without having to disconnect Previous board testers had multiplexing schemes to reduce the number of pin drivers required With the small size and power consumption of the monolithic EL2021 a driver per node with little or no multiplexing becomes practical Since only a few pins of ``bed-ofnails'' board testers need be active at any given time the powerdown feature saves substantial power in large systems Applications Loaded circuit board testers Digital testers Programmable 4-quadrant power supplies Block Diagram Ordering Information Part No Temp Range Package Outline CerDIP MDP0031 EL2021CJ 0 C to a 75 C Connection Diagram 18-Pin DIP Package 2021 - 2 Truth Table E 0 0 2021 - 1 November 1993 Rev F OE 0 0 1 X Data 0 1 X X VOUT VCL VCH High-Z Undefined Comments Active Active Third State Power-down Top View 0 1 Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation Patent pending 1988 Elantec Inc EL2021C Monolithic Pin Driver Absolute Maximum Ratings (TA e 25 C) Va Vb B a Bb Sense a Senseb E VSR OE Data VCH VCL Supply Voltage Supply Voltage Supply Voltages Input Voltages Input Voltages Input Voltages Input Voltages b 0 3V to a 16V 0 03V to b16V Vb to V a (b2V a B a ) to (0 3V a B a ) (b0 3V a Bb) to (2V a Bb) b 0 3 to a 6V Bb to B a and Vb to V a Sense Out VOUT Drive a Driveb TJ TA TST PD Output Current b 10 mA to a 10 mA b 45 mA to a 45 mA Output Currents Junction Temperature 150 C Operating Ambient Temperature Range 0 C to a 75 C b 65 C to a 150 C Storage Temperature Power Dissipation (TA e 25 C) (See Curves) 1 8W Important Note All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore TJ e TC e TA Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002 100% production tested at TA e 25 C and QA sample tested at TA e 25 C TMAX and TMIN per QA test plan QCX0002 QA sample tested per QA test plan QCX0002 Parameter is guaranteed (but not tested) by Design and Characterization Data Parameter is typical value at TA e 25 C for information purposes only DC Electrical Characteristics TA e 25 C V a e 15 Vb e b10V B a e VCH a 3 6V Bb e VCL b3 6V No Load Data and OE levels are L e 2 0V and H e 3 0V (CMOS thresholds) E levels are L e 1 5V and H e 3 5V All tests done using 2N2222 and 2N2907 output transistors with Betal40 IC e 400 mA and Betal27 IC e 500 mA and VCE e 3 1V OE and E low Parameter IS Description V a -Supply Currents Conditions VCH e 5V VCL e 0 VSR e 2 5V Data e H or L VCH e 11V VCL e b6V VSR e 5V Data e H or L VCH e b6V VCL e 11V VSR a 2 5V Data e H or L VCH e 5V VCL e 0V VSR e 2 5V Data e H or L E e H VCH e b1V to a 7 5V VCL e 0V VSR e 5V Data e H or L VCL e b3 5V to a 3 5V VCH e 0V VSR e 5V Data e H or L VCH e 5V VCL e 0V VSR e 5V Data e 0 or 5V Min Typ Max 15 21 15 0 b 20 Test Units Level I IV IV I I I I I I I IV IV mA mA mA mA mA mA mA mA mA TD is 2 7in mA mA mA 25 33 25 05 5 30 45 30 25 20 20 50 20 20 20 20 20 IS disabled V a -Supply Currents IVCH IVCL IData IOE IE IVSR gIsense VCH Input Current VCL Input Current Data Input Current OE Input Current E Input Current VSR Input Current Sense Input Currents b 20 b 5 b 50 5 5 2 2 5 5 VCH e 5V VCL e 0V VSR e 5V Data e L OE e 0V or 5V b20 VCH e 5V VCL e 0V VSR e 5V Data e L E e 0V or 5V VCH e 5V VCL e 0V Data e L VSR e 0V or 5V VCH e 5V VCL e 0V VSR e 5V Data e 0V or 5V b 20 b 20 b 20 b 20 IB a IBb B a Bb Input Currents VCH e 5V VCL e 0V Data e L VSR e 5V 2 TD is 1 1in EL2021C Monolithic Pin Driver DC Electrical Characteristics TA e 25 C V a e 15 Vb e b10V B a e VCH a 3 6V Bb e VCL b3 6V No Load Data and OE levels are L e 2 0V and H e 3 0V (CMOS thresholds) E levels are L e 1 5V and H e 3 5V All tests done using 2N2222 and 2N2907 output transistors Contd with Betal40 IC e 400 mA and Betal27 IC e 500 mA and VCE e 3 1V OE and E low Parameter VO Description Output Voltage Conditions Min Typ Max Test Units Level V a e 14 5V Vb e b9 5V VCH e 5V VCL e 0 VSR e 1V Data e L b 50 Output Current e b100 mA 0 mA or a 100 mA b 300 Output Current e b400 mA or a 400 mA b 600 Output Current e b500 mA or a 500 mA VCH e 5V VCL e 0 VSR e 1V Data e H 4 95 Output Current e b100 mA 0 mA or a 100 mA 47 Output Current e b400 mA or a 400 mA 44 Output Current e b500 mA or a 500 mA VCH e 11V VCL e b6V VSR e 1V IOUT e 0 Data e L b6 1 VCH e 11V VCL e b6V VSR e 1V IOUT e 0 Data e H 10 9 400 450 50 300 600 5 05 53 56 b5 9 11 1 600 I I I I I I I I I I I I I mV mV mV V V V V V mA mA V V mA Isense a Isenseb VO sense a Isense Threshold VCH e 5V VCL e 0 VSR e 2 5V Rsense e 1X Data e H b Isense Threshold VCH e 5V VCL e 0 VSR e 2 5V Rsense e 1X Data e L b 400 b 450 b 600 Sense Out Levels IOUT TRI High-Impedance VCH e 5V VCL e 0 VSR e 2 5V Data e L OE e H Output Leakage Output Voltage e b2 5V or a 7 5V b 100 5 100 AC Electrical Characteristics DC test conditions apply except where noted For AC tests RL e 1k CL e 200 pF Delay times are measured from OE or Data crossing 2 5V VCH e 5V VCL e 0 Parameter SR a SRb Description a Slew Rate b Slew Rate Conditions Data L to H Output from 0 5V to 4 5V VSR e 1V VSR e 3V Data H to L Output from 4 5V to 0 5V VSR e 1V VSR e 3V (SR a )b(SRb) (SR a ) a (SRb) Min 80 150 b 80 b 150 b 10 b 20 Typ 100 240 b 100 b 240 Max 120 360 b 120 b 360 Test Level I I I I I IV I I IV IV I I I I I I I Units V ms V ms V ms V ms % % ns ns ns ns mV mV mV ns ns ns ns TD is 3 2in SRSYM Tpd Ts OS Slew Rate Symmetry Propagation Delay Settling Time Overshoot ( VSR e 1V VSR e 2V 10 20 9 9 11 5 11 5 30 30 Data L to H Output to 0 2V VSR e 2 5V Data H to L Output to 4 8V VSR e 2 5V VSR e 5V Data L to H Output 4 5V to 5Vg0 2V VSR e 5V Data H to L Output 0 5V to g0 2V VSR e 1V Data L to H or H to L VSR e 1V OE H to L Data e L RL to 5V VSR e 1V OE H to L Data e H RL to 0V VSR e 2 5V OE H to L CL e 50 pF RL to 5V Data e L Output to 3 5V RL to 0V Data e H Output to 1 5V VSR e 2 5V OE L to H CL e 50 pF Data e L RL to 5V Output to 0 5V Data e H RL to 0V Output to 4 5V 3 65 65 b 300 b 300 b 300 300 300 300 50 50 50 50 Tpda Propagation Delay High-Z to Active Propagation Delay Active to High-Z Tpdh TD is 2 7in VCH e 5V VCL e 0 VSR e 2 5V Data L or H Output Current e b350 mA or a 350 mA Output Current e b550 mA or a 550 mA 0 35 06 50 EL2021C Monolithic Pin Driver Pin Description Table Pin 1 2 Name GND E System ground Enable control input A logic low allows normal operation a logic high puts the device into power down mode No output levels are defined in powerdown nor does the output behave as a high impedance Output Enable input A logic low sets the output to low-impedance driver mode a logic high places the output into a high-impedance state Lower analog control input When Data e OE e E e L the VCL level is output as VOUT (assuming VCL k VCH) System power supply The EL2021 uses this pin as a negative output current monitor connection Little current is drawn from this pin transient or static Negative output current monitor input Negative power supply Because all negative output drive currents come from this pin (as much as 60 mA transiently) good bypassing is essential Output to external pnp transistor base High-current input and output depending on OE Output to external npn transistor base Logic output which signals that a high a or b output current is flowing Positive power supply Like Vb it should be well bypassed Positive output current monitor input System power supply similar to Bb Higher analog control input When Data e H and OE e E e L the VCH level is output as VOUT (assuming VCH l VCL) Slew rate control input A 1V level on this pin causes the output to slew at 100 V ms 0 5V causes a slew rate of 50 V ms etc Output level control input This pin digitally selects VCL or VCH as the output voltage when OE e E e L Not Connected Description 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 OE VCL Bb Isenseb Vb Driveb VOUT Drive a Sense Out Va Isense a Ba VCH VSR Data NC 4 EL2021C Monolithic Pin Driver Typical Performance Curves 2021 - 3 2021 - 4 2021 - 5 Family of output waveshapes ECL TTL CMOS HCMOS with C1 e 50 pF VSR e 1V Family of output waveshapes ECL TTL CMOS HCMOS with C1 e 200 pF VSR e 1V Output waveshapes with 5 MHz data rate C1 e 50 pF VSR e 4V 2021 - 6 2021 - 7 2021 - 8 Family of output waveshapes ECL TTL CMOS HCMOS with C1 e 200 pF VSR e 1V and overcompensated with 22 pF from each drive pin to ground Family of output waveshapes from active H L to high-impedance H L Family of output waveshapes from high-impedance H L to active H L 2021 - 9 2021 - 10 Family of a output edges 0V to 5V for VSR e 0 5V 1V 2V 3V 5V Family of output edges 5V to 0V or VSR e 0 5V 1V 2V 3V 5V 5 EL2021C Monolithic Pin Driver Typical Performance Curves Contd Overshoot vs VSR Overshoot vs VSR Slew Rate vs VSR VOUT vs Load Current Supply Current vs Supply Voltage Tri-State Leakage vs Output Voltage Supply Current vs VSR Power Dissipation vs Temperature 2021 - 11 6 EL2021C Monolithic Pin Driver Applications Information Output Stage To meet the requirements of low output impedance wide bandwidth and large capacitive load driving capability the EL2021 has a fairly exotic output stage Figure 1 shows a simplified schematic of the circuit only applicable in normal low impedance mode External transistors are used to handle the large load currents and peak power dissipations Since there is no need for good AC crossover distortion performance in a pin driver the output transistors are operated class C That is for small output currents neither output transistor will conduct bias current and when load currents do flow one of the devices is off This is accomplished by biasing the output transistors from Schottky diodes D1 and D2 In operation the diode forward voltage is about 0 4V whereas the ``on'' output transistor will have a VBE of 0 6V This leaves only 0 2V across the ``off'' transistor's base-emitter junction not nearly enough to cause bias currents to flow in it Schottky diodes have a temperature drift similar to silicon transistors so the class C bias maintains over temperature One caution is that the diodes are in the IC package and are thermally separate from the transistors so there can exist temperature differences between packages that can cause thermal runaway Runaway is avoided as long as the external transistors are not hotter than the EL2021 package by more than 80 C The only way runaway has been induced as of this writing is to use ``freeze spray'' on the IC package while the output transistors are very hot This circuit allows the external transistors to run from B a and B b supplies that are of less voltage than V a and V b to conserve power Reducing Bg supplies also reduces dissipations in the output devices themselves B a is typically made K volts more than VCH and B b made K volts more negative than VCL Ideally K is made as small as possible to minimize output transistor dissipation but two factors limit how small K can be These factors are both related to the fact that transistors have two collector resistance numbers ``hard'' and ``soft'' saturation resistance As a transistor begins to saturate at high collector currents and small collector-emitter voltages minority carriers begin to be generated from the base-collector junction These carriers act as more collector dopant and actually reduce effective series collector resistance At conditions of heavy saturation the collector is flooded with minority carriers and exhibits minimum collector resistance In this way small geometry transistors like the 2N2222 and 2N2907 devices have excellent collector-emitter voltage drops at high currents but are actually still in heavy saturation for 1V2V drops This ``soft'' saturation shows up as reduced beta at high currents and moderate VCE's as well as very poor AC performance A transistor may exhibit an ft of only 2 MHz in soft saturation when like the 2N2222 it gives 300 MHz in non-saturated mode The EL2021 requires the output transistors to have an ft of at least 200 MHz to prevent degradation in overshoot slew rate into heavy loads and tolerance of heavy output capacitance With a K of 3 2V and 1X collector resistors almost all 2N2222 and 2N2907 devices perform well but we have obtained devices from some vendors where the beta does indeed fall permaturely at reduced VCE and high currents It is important to characterize the external devices for the service that the EL2021 will be expected to provide The output stage of the EL2021 does not ring appreciably into a capacitive load in quiescent conditions but it does ring while it slews This is an unusual characteristic but the output slews monotonically and the slew ``ripple'' does not cause problems in use The slew ripple does cause a similar ``ripple'' in the overshoot-vs-VSR characteristic the overshoot may decrease for slightly increasing VSR then increase again for larger VSR's again The overshoot-vs-VSR graphs 7 2021 - 12 Figure 1 Simplified Output Stage (Normal Mode) EL2021C Monolithic Pin Driver Applications Information Contd presented in this data sheet thus reflect the range of overshoot rather than one particular device's wavy curve The circuit works properly for AC signals up to 500 V ms Above this slew rate the buffer cannot keep up and the external transistors may turn on transiently Because of the bootstrap action the output capacitance is less than 10 pF up to 10 MHz of small-signal bandwidth and 300 V ms slew rate increasing beyond these values Adding overcompensation capacitors will degrade the slew rate that the output can withstand before current is drawn It is sometime necessary to provide a ``snubber'' network-a series R and C b to provide a local R F impedance for the buffer to look into 330X and 56 pF should serve Also it is well to provide some DC path to ground (47k for instance) to bias the output stage when no actual circuit is connected to the EL2021 in high-impedance mode The typical 2N2222 and 2N2907 will deliver 750 mA into a short-circuit This puts four watts of dissipation into the 2N2222 for VCH e 5V The npn can dissipate this power for a few tenths of a second as long as a metal-base TO-39 package is used The small or non-metal-based packages have short thermal time constants and high thermal resistances so they should withstand shorts for only a few milliseconds The Sense Out signal should be used to control OE or reduce VCH and VCL to relieve the output devices from overcurrent conditions Transistors such as the MJE200 and MJE210 have very much improved collector resistances and high-current beta compared to the 2N2222 and 2N2907 Their ft's are almost as good and sustain at higher currents and high-current output accuracy will improve They allow a K of 2V to reduce dissipations further but short-circuit currents will be as much as two amperes The geometries of these transistors are larger and the added transistor capacitances will slow the maximum Slew Rates that the EL2021 can provide If transistors with ft's less than 200 MHz are used the EL2021 will need to be overcompensated This is accomplished by connecting equal capacitors from the Drive pins to ground These capacitors will range from 10 pF to 50 pF The overcompensation will slow the maximum slew rate but it will improve the overshoot and reactive load driving capability and can be considered a useful technique Figure 2 shows the equivalent output stage schematic when the circuit is in high-impedance mode (OE e H) The external transistors have their base-emitter junctions each reverse-biased by a Schottky diode drop A buffer amplifier copies the output voltage to give a bootstrapped bias for the Schottky stack This scheme guarantees that the external transistors will be off for any output level and the output leakage current is simply the bias current of the buffer 2021 - 13 Figure 2 Simplified Output Stage (High-Impedance Mode) Power Supplies In typical operation V a and V b can be as much as g15V and as little as VCH a 3V and VCL b 3V respectively When driving heavy output currents however it is wise to have 5V of headroom above VCH and below VCL to ensure no saturation of devices within the EL2021 and attendent waveshape distortions Thus for VCH e 5V and VCL e b 2V minimum operating voltages are a 10 b 7V It is very important to bypass the supply terminals with low-inductance 8 EL2021C Monolithic Pin Driver Applications Information Contd capacitors to ground since the full base drive currents of the output transistors are derived from these supplies Because the pulse currents can reach 60 mA the capacitors should be at least a microfarad 4 7 mF tantalum are ideal and require no small bypasses in parallel The response of the Sense Out can be thought of as slow attack and fast decay A continuous overcurrent condition must last for at least 2 ms before Sense Out will go high but will clear to low only about 200 ns after the overcurrent is withdrawn This allows transient currents due to slewing capacitive load to not generate a flag On the other hand the output transistors will not be damaged with only a 2 ms system reaction time to a short-circuit B a and B b can be any voltage within V a and V b and some amount previously discussed above VCH and below VCL If VCH or VCL exceeds B a or B b very large internal fault currents can flow when the EL2021 attempts to bring an output transistor's base beyond the collector voltage The bypassing care of the Vg lines apply to the Bg lines as well as the fact that ampere currents can occur Large (100 mF - 500 mF) capacitors should be used to bypass perhaps every tenth EL2021 The VCH VCL Data and OE lines should be driven locally so as to not pick up magnetic interference from the output The inductance of interconnects to these lines can allow coupling to cause waveshape anomalies or even oscillations If long lines are unavoidable local 1k resistors or 50 pF - 100 pF capacitors to ground can also serve the purpuse Construction Practices The major cautions in connecting to the EL2021 involve magnetic rather than capacitive parasitic concerns The circuits can output as much as 100 A ms Even with normal Slew Rates and moderately large capacitive loads the dI dT can cause magnetic fields in harmless looking wires to fill adjacent lines with noise and sometimes ringing or even sustained feedback Thus rules for wiring the EL2021 are (a) Keep leads short and large Short wires are less inductive as are wires with large surface area The large surface area also reduces skin resistance at high frequencies important at high currents (at 100 MHz current penetrates only a few microns in metals) (b) Use a ground plane Due to inductance and skin effect ``ground'' voltages will be different only inches apart on a copper ground plane Individual wires do not create ground at high frequencies The common ``star'' ground is a very bad idea for high-current and high-frequency circuits (c) Dress all wires against the ground plane The magnetic fields that the wires would have generated will be intercepted by the ground plane and absorbed thus reducing the wire's effective inductance The capacitance added by this method is not important to EL2021 operation (d) The external transistors should have short interconnects to the EL2021 the collector shunt resistors and the bypass capacitors As previously stated the shunt resistors must not be wire wound because of their inductance Data Pin The slew rate of the input to the Data pin should be kept less than 1000 V ms Some feedthrough can occur for large Slew Rates which will distort the output waveshape A 1k - 2k resistor in series with the data pin will reduce feedthrough Current Sense The output current is sensed by comparing the voltage dropped across the external shunt resistors to an internal 0 45V reference The center of the trip level is adjusted for the particular output transistor betas listed in the data specifications Transistors with less beta at high currents will cause the sense comparators to trip at slightly higher output currents The 1X shunt resistors should be non-inductive The family of wirewound resistors called ``non-inductive'' are too inductive for these shunts 9 EL2021C Monolithic Pin Driver Applications Information Contd (e) The bypass capacitors should have low series resistance and inductance but should not have a high Q This may seem contradictory but a 4 7 mF tantalum capacitor seems to work the best An electrolytic capacitor should be added to help bolster the supply levels in the 0 1 ms - 1 ms after a transition No small capacitors are needed in parallel with the tantalums The bypasses' ground returns are best connected to the area of ground inside the package outline to reduce the circulating current path length if possible Using the EL2021 without External Transistors By connecting both drive pins to the output pin the EL2021 can be used as a stand-alone driver not requiring the external transistors The EL2021 is good for more than 50 mA in this mode The output impedance rises to 12X however and the current sense and high-impedance mode are not available The ripple seen in slew edges using the external transistors is largely absent from the standalone waveshapes and overshoot is markedly improved at VSR l 1V especially with large capacitive loads Typical Applications 100 V ms High-Current Pin Driver Outputting TTL Levels 2021 - 14 10 BLANK 11 EL2021C EL2021C Monolithic Pin Driver Package Outline MDP0025 Rev A 18-Lead CerDIP General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement WARNING Life Support Policy November 1993 Rev F Elantec Inc 1996 Tarob Court Milpitas CA 95035 Telephone (408) 945-1323 (800) 333-6314 Fax (408) 945-9305 European Office 44-71-482-4596 12 Elantec Inc products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec Inc Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death Users contemplating application of Elantec Inc products in Life Support Systems are requested to contact Elantec Inc factory headquarters to establish suitable terms conditions for these applications Elantec Inc 's warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages Printed in U S A |
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